Modern semiconductors are assembled in either wirebonded or flipchip packages. In either case, the package provides the interconnect between the fine geometries of the silicon design and wider pitches at the circuit board level. The package also serves as environmental protection for the silicon die. With increasing IO (Input/Output) densities and total IO counts, faster signaling speeds, and sharper IO slew rates, the package interconnect has become an integral part of both the silicon and board level design considerations. Specifically, it has forced the need for packages which are highly tuned and customized to a particular silicon design and board application. This level of customization may result in highly detailed studies and extensive development schedules during package and silicon co-design.
Various silicon and package co-design environments exist with varying levels of automation. Invariably, these conventional solutions are comprised of three, sometimes four, components (see, e.g., FIG. 1). Each major component of the solution, namely the Silicon Design, the Package Design, the Board Design, and the Electrical Modeling, are completed by appropriate engineering teams. Use of automation is commonly used across all four areas. The level of automation often propagates results across each of the four areas. For example, the silicon designer may view the package design in-place as the chip IOs are assigned. Likewise, the package designer may view the silicon design and locations of IO circuits in-place so that the positioning of package wirebond fingers of flipchip bump pads can be optimized. Since there is a high degree of interaction in each of the four areas, the work flow for converging on a solution requires piecemeal progress on each topic. In other words, the total solution is achieved by locating IO circuits in the silicon design, completing components of the package design, conducting electrical modeling, conducting board layout studies, conducting further optimization of the silicon, making further changes to the package, re-visiting the electrical modeling, and so on (see, e.g., FIG. 2). It is noteworthy that there is no fixed or exact sequencing of effort in the areas of Silicon Design, Package Design, Board Design, or Electrical Modeling. Design specific constraints often dictate the number of times and at which points each area is revisited.
The conventional approaches ensure all Package Design, Silicon Design, Electrical Modeling, and Board Layout considerations are addressed collectively. The level of closure in each step of the work flow may be varied. For example, a very rough silicon IO assignment may be completed before conducting some initial package design work. Likewise, a near final IO assignment may be conducted before some initial package design work starts. This level of granularity may be varied with each application of the conventional approaches for a specific Silicon and Package co-design exercise. The level of granularity may be dictated by the complexity of constraints in each of these four areas.
However, the conventional approaches have the following disadvantages. First, in practice, the conventional work flow may be highly iterative. For example, the silicon designer may opt to place a specific SERDES (Serializer/Deserializer) high-speed IO interface at a particular die location. This may force the package designer to optimize the respective region of the package design. As a side-effect, this may require other components of the package design to be adjusted. Undesirable impacts of these changes may only be exposed during electrical modeling, which may force the silicon designer to move other IO circuits on the die, or reconsider the necessity of the specific SERDES placement location. Moreover, the conventional approaches may result in long Silicon and Package co-design development cycles since each area need be re-evaluated multiple times, and in some cases, completely restarted. Furthermore, the conventional work flow has no closed loop controllability and as a result, it becomes difficult to predict cycle times for a given Silicon and Package co-design exercise. In addition, supporting such a work flow requires extensive resourcing to service the many and often fine grained iterations between Silicon, Package, Board Designs and Electrical Modeling. Resources must be assigned in all four areas, and permanently available to re-evaluate changes as required. The manpower resourcing of the conventional approaches is therefore very costly. Further, extensive tool automation and tool investment are required to assist in cross-propagating Silicon, Package, Board, and Electrical data. Invariably, design teams use a combination of off-the-shelf EDA (Electronic Design Automation) tools coupled with their own internal utilities to bridge data from one system to another. This often requires costly tool investment and development.
Thus, it would be desirable to provide a package and silicon co-design solution to the foregoing-described problems.